Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modem electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM functions as a read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to read-only memory (ROM), which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of ROM that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. EEPROM comprise a memory array which includes a large number of memory cells having electrically isolated gates. Data is stored in the memory cells in the form of charge on the floating gates or floating nodes associated with the gates. Each of the cells within an EEPROM memory array can be electrically programmed in a random basis by charging the floating node. The charge can also be randomly removed from the floating node by an erase operation. Charge is transported to or removed from the individual floating nodes by specialized programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that is typically erased and reprogrammed in blocks instead of a single bit or one byte (8 or 9 bits) at a time. A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor (FET) capable of holding a charge. The data in a cell is determined by the presence or absence of the charge in the floating gate/charge trapping layer. The cells are usually grouped into sections called “erase blocks.” Each of the cells within an erase block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation.
The memory cells of both an EEPROM memory array and a Flash memory array are typically arranged into either a “NOR” architecture (each cell directly coupled to a bit line) or a “NAND” architecture (cells coupled into “strings” of cells, such that each cell is coupled indirectly to a bit line and requires activating the other cells of the string for access).
Floating gate memory cells are typically programmed by injecting electrons to the floating gate by channel hot carrier injection (CHE), typically placing the cell in a high threshold voltage state. Floating gate memory cells can also be erased by hot hole injection from the substrate. Alternatively, floating gate memory cells can be programmed and erased by electron tunneling to and from the substrate by Fowler-Nordheim tunneling to put the cell in a programmed or erased threshold state. Both mechanisms require the generation of high positive and negative voltages in the memory device and can place high fields across the gate insulation layers with resulting adverse effects in device characteristics and reliability.
A problem with CHE, hot hole injection and Fowler-Nordheim tunneling is that the high energy required for their operation damages the oxide interfacing silicon substrate, reducing memory cell retention, endurance, and degrading transconductance of the FET. In particular, the tunnel insulation layer, which is placed between the channel and the floating node/charge trapping layer is typically damaged by the programming process by having hot carriers injected or tunneled through it. As high control fields are also typically asserted on the channel during writing and erasing through the tunnel insulation layer by the application of voltage to the control gate of the memory cell, damage to the tunnel insulator by the hot carrier injection or high fluence tunneling process can significantly affect device characteristics. Hot carrier injection can generate interface states, degrade device transconductance, and enhance device leakage via enhanced short channel effect, besides affecting charge retention and read-disturb. Hot hole injection can generate fixed charge trapping centers in the tunneling insulators and associated defects in the trapping layer, thus breaking stable bonds and eventually degrading the insulator/dielectric properties of the device. For a conventional Flash or SONOS non-volatile memory device, the same control gate is also used during a read operation as a FET to read the state of the memory cell. When the tunnel insulator (also known as the tunnel oxide) is degraded, the read characteristics of the memory cell are also degraded due to the transconductance degradation and enhanced leakage. This affects the read speed of the memory cell.
An additional problem in Flash and SONOS memory cell arrays is that voltage scalability affects the minimum cell size, and consequently the overall memory density of any resulting array. As integrated circuit processing techniques improve, manufacturers try to reduce the feature sizes of the devices produced and thus increase the density of the IC circuits and memory arrays. In modem IC circuits and memory arrays, as SONOS transistors and floating gate memory cells are scaled to smaller feature sizes, the device characteristics of the component transistors and floating gate memory cells can alter and leave the resulting IC or memory device non-functional. These issues include, but are not limited to, short channel effect, signal cross-talk, device programming and operating voltages, reduced logic windows, oxide punch-through, and charge leakage and retention.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for methods and apparatus for a non-volatile memory cell that allows for feature and voltage scaling, prevents read degradation while providing enhanced retention, speed, endurance, and exhibits increased device integrity.